A ceramic via disk is a circular alumina substrate that includes a large number of closely spaced, precisely located holes or vias formed therethrough. These vias are filled with conductive material to provide isolated conductive regions through the insulating ceramic substrate. The disk can be scaled to match the size of a semiconductor wafer.
Ceramic via disks are well-suited for probe card applications, specifically to facilitate space transformation. The probe card is a custom-designed interface that provides electrical signal paths between the test system and circuits on a wafer, thereby permitting the testing and validation of the circuits at wafer level, before the wafers are cut into individual integrated circuits and subsequently packaged. Probe cards typically include contact elements or probe assemblies (needles, wires, probes, etc) along with space transformers, interposers, and PCBs/stiffeners.
The function of the space transformer is to enable contact between the bond pads on a single semiconductor device (die), a plurality of dice, or over an entire wafer (if wafer-scale integration is employed for the unit under test) and then route the electrical connection to the terminals found on printed circuit boards.
The space transformer may be constructed using many formats including, but not limited to, multi-layer tape cast ceramics, single-layer fully-fired (hardened) ceramics with thin or thick film build-up techniques, printed circuit boards or BT Resin cores with build-up layers (e.g., multi-layer organic), where each offers alternating layers of circuit metalization and dielectric, with metalized through vias providing connection between each of the layers.
One problem associated with these techniques is an inability to maintain sufficient planarity and surface parallelism as dimensions increase beyond 4-6 inches in length or width. In addition, as thickness increases, vertical routing requires the use of multiple dielectric layers and the maintenance of electrical continuity and support of high performance signals becomes a challenge.
Ceramic based multi-layer circuit boards provide superior electrical properties as compared to organic printed circuit boards and are employed in higher performance applications. One commonly practiced technology for fabricating multi-layer substrates uses co-fired tape cast ceramics. The co-fired ceramic structure is a monolithic ceramic substrate after it has been completely fired. According to a high temperature version of this technique, commonly known as high temperature co-fired ceramic (HTCC), a mixture of 90%-95% alumina (Al2O3) and glass is fired at about 1,600° C. with tungsten or molybdenum-based metal paste. Alternatively, a high-glass concentration ceramic, commonly known as low temperature co-fired ceramic (LTCC), is fired at a lower temperature of about 900 to 1000° C. with gold, silver, copper, or silver-palladium based paste. In general, a ceramic powder and organic binder are mixed, extruded, and cut into malleable sheets. Since the sheets are easily worked, the vias are punched through the sheets and filled with the selected conductive paste. Conductor patterns are screen printed on one side. The sheet can be fired alone or in a stacked configuration under high temperature and pressure to form a sintered component.
However, the manufacture of multi-layer substrates using cast ceramic, or “green tape,” introduces its own problems. This technology possesses a number of disadvantages due to potential variation in the alignment of conductive patterns, vias and cavities which limit interconnect density. These problems are created by the differential shrinkage within and between the individual layers of the ceramic material from which the multi-layer substrate is formed. Also, the surface roughness of the tape cast ceramics limit electrical performance. Further, since tape cast or green sheet ceramics can contain between 8% and 40% binders, the purity levels of the processed ceramics are not tightly controlled, leading to a compromise in electrical performance. In addition, the intrinsic shrinkage of the tape cast ceramic impacts the filling of vias such that voiding and/or other discontinuities become more challenging as the thickness of the substrate increases. See, e.g., Integrated Circuit Engineering Corporation, Ch. 11: Interconnect Substrate Technologies, pp 1130 to 1137, viewable at: www.smithsonianchips.si.edu/ice/cd/PKG_BK/CHAPT—11.PDF, the disclosure of which is incorporated by reference herein in its entirety.
If hardened ceramic substrates are employed, they can be drilled with a laser or other suitable method to form a plurality of vias. Molybdenum or tungsten ink can then be used to both print the wire patterns and fill the vias. However, this process may leave a significant number of electrically non-conductive “open” vias that render them unusable. See, e.g., U.S. Pat. No. 6,114,240, U.S. Pat. No. 6,215,321, and U.S. Pat. No. 6,852,627. Other via filling processes have also been described. U.S. Pat. No. 6,852,627, for example, describes the use of electroless plating processes to fill vias. Other patents, for example, U.S. Pat. No. 5,287,619 and U.S. Pat. No. 5,440,805, describe the use of electroplating processes to fill vias. The disclosures of the above six patents are herein incorporated by reference in their entireties.
Due to the above-described problems, via disks manufactured using co-fired technology have very low yields, often not exceeding 25%. These low yields result in long lead times, as well as increased costs.